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NCP3125 4 A Synchronous PWM Switching Converter
The NCP3125 is a flexible synchronous PWM Switching Buck Regulator. The NCP3125 is capable of producing output voltages as low as 0.8 V. The NCP3125 also incorporates voltage mode control. To reduce the number of external components, a number of features are internally set including switching frequency. The NCP3125 is currently available in an SOIC-8 package.
Features
8 1 SOIC-8 NB D SUFFIX CASE 751
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8 3125 ALYWXG G
* * * * * * * * * * * * * * *
4.5 V to 13.2 V Operating Input Voltage Range 60 mW High-Side, 36 mW Low-Side Switches Output Voltage Adjustable to 0.8 V 4 A Continuous Output Current Fixed 350 kHz PWM Operation 1.0% Initial Output Accuracy 75% Max Duty Ratio Short-Circuit Protection Programmable Current Limit This is a Pb-Free Device Set Top Boxes DVD Drives and HDD LCD Monitors and TVs Cable Modems Telecom / Networking / Datacom Equipment
1
3125 A L Y W G
= Specific Device Code = Assembly Location = Wafer Lot = Year/ = Work Week = Pb-Free Package
Typical Application
PIN CONNECTIONS
PGND FB COMP AGND (Top View) 1 VSW ISET VIN BST
See detailed ordering and shipping information in the package dimensions section on page 21 of this data sheet.
ORDERING INFORMATION
100 4.5 V - 13.2 V VIN BST VSW 3.3 V EFFICIENCY (%) 95 90 85 80 75 70 65 0 0.5 1 1.5 2 2.5 3 OUTPUT CURRENT (A) 3.5 4 5V
PGND NCP3125 ISET COMP FB1 AGND
Figure 1. Typical Application Circuit
Figure 2. Efficiency (VIN = 12 V) vs. Load Current
(c) Semiconductor Components Industries, LLC, 2010
April, 2010 - Rev. 1
1
Publication Order Number: NCP3125/D
NCP3125
CIRCUIT DESCRIPTION
BST + - - + 10 mA Fault + 0.8 V FB - - S Counter DtoA Clock Ramp OSC VREG OSC + - Fault 0.7 V Count Latch & Logic + - - + + - 2V VCC VSW + PWM Comp R PWM OUT Q Fault UVLO POR + - VOCTH VIN
VREF
Latch
SCP
COMP
AGND
Figure 3. NCP3125 Block Diagram
ISET
PGND
Table 1. PIN DESCRIPTION
Pin 1 2 Pin Name PGND FB Description The PGND pin is the high current ground pin for the low-side MOSFET and the drivers. The pin should be soldered to a large copper area to reduce thermal resistance. Inverting input to the Operational Transconductance Amplifier (OTA). The FB pin in conjunction with the external compensation, serves to stabilize and achieve the desired output voltage with voltage mode control. COMP pin is used to compensate the OTA which stabilizes the operation of the converter stage. Place compensation components as close to the converter as possible. The AGND pin serves as small-signal ground. All small-signal ground paths should connect to the AGND pin at a single point, avoiding any high current ground returns. Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired input voltage to this pin (cathode connected to BST pin). Connect a capacitor (CBST) between this pin and the VSW pin. Typical values for CBST range from 1 nF to 10 nF. Ensure that CBST is placed near the IC. The VIN pin powers the internal control circuitry and is monitored by an undervoltage comparator. The VIN pin is also connected to the internal power NMOSFET switches. The VIN pin has high dI/dt edges and must be decoupled to PGND pin close to the pin of the device. Current set pin and bottom gate MOSFET driver. Place a resistor to ground to set the current limit of the converter. The VSW pin is the connection of the drain and source of the internal N-MOSFETs. The VSW pin swings from VIN when the high side switch is on to small negative voltages when the low side switch is on with high dV/dt transitions.
3 4 5
COMP AGND BST
6
VIN
7 8
ISET VSW
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Table 2. MAXIMUM RATINGS
Rating Main Supply Voltage Input Bootstrap Supply Voltage vs GND Bootstrap Supply Voltage vs Ground (spikes 50 ns) Bootstrap Pin Voltage vs VSW High Side Switch Max DC Current VSW Pin Voltage Switching Node Voltage Excursion (200 mA) Switch Pin voltage (spikes < 50 ns) FB Pin Voltage COMP/DISABLE Low Side Driver Pin Voltage Low Side Driver Pin Voltage (spikes v 200 ns) Rating Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case Storage Temperature Range Junction Operating Temperature Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb-Free (Note 2) (Note 3) Symbol VIN VBST VBST spike VBST-VSW IVSW VSW VSWLIM VSWtr VFB VCOMP/DIS VISET VISET Spike Symbol RqJA RqJC Tstg TJ RF Min -0.3 -0.3 -5.0 -0.3 0 -0.3 -2.0 -5.0 -0.3 -0.3 -0.3 -2 Rating 110 183 170 -55 to 150 -40 to 125 260 peak Max 15 15 35 15 4 30 35 40 5.5 < VCC 5.5 < VCC 15 < VCC 15 < VCC Unit V V V V A V V V V V V V Unit C/W C/W C C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The maximum package power dissipation limit must not be exceeded. 2. The value of qJA is measured with the device mounted on 1 in2 FR-4 board with 1 oz. copper, in a still air environment with TA = 25C. The value in any given application depends on the user's specific board design. 3. The value of qJA is measured with the device mounted on minimum footprint, in a still air environment with TA = 25C. The value in any given application depends on the user's specific board design. 4. 60-180 seconds minimum above 237C.
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Table 3. ELECTRICAL CHARACTERISTICS (-40C < TJ < 125C; VIN = 12 V, BST-VSW = 12 V, BST = 12 V, VSW = 24 V, for
Characteristic Input Voltage Range Boost Voltage Range SUPPLY CURRENT Quiescent Supply Current Shutdown Supply Current Boost Quiescent Current UNDER VOLTAGE LOCKOUT VIN UVLO Threshold VIN UVLO Hysteresis SWITCHING REGULATOR VFB Feedback Voltage, Control Loop in Regulation Oscillator Frequency Ramp-Amplitude Voltage Minimum Duty Ratio Maximum Duty Ratio PWM COMPENSATION Transconductance Open Loop DC Gain Output Source Current Output Sink Current Input Bias Current ENABLE Enable Threshold SOFT-START Delay to Soft-Start SS Source Current Switch Over Threshold OVER-CURRENT PROTECTION OCSET Current Source OC Switch-Over Threshold Fixed OC Threshold PWM OUTPUT STAGE High-Side Switch On-Resistance Low-Side Switch On-Resistance 5. Guaranteed by design. VIN = 12 V (Note 5) VIN = 5 V (Note 5) VIN = 12 V (Note 5) VIN = 5 V (Note 5) 60 80 36 45 75 100 40 50 mW mW Sourced from ISET pin, before SS - - - 10 700 375 - - mA mV mV VFB < 0.8 V VFB = 0.8 V 3 - - - 10.5 100 15 - - ms mA % of Vref 0.3 0.4 0.5 V CO = 1 nF VFB < 0.8 V VFB > 0.8 V 3.0 55 60 60 - - 70 125 125 0.160 5 - 200 200 1.0 mS dB mA mA TJ = 0 to 25C, 4.5 V < VCC < 13.2 V -40C v TJ v 125C, 4.5 v VCC v 13.2 V TJ = 0 to 25C, 4.5 V < VCC < 13.2 V -40C v TJ v 125C, 4.5 v VCC v 13.2 V 792 784 300 290 0.8 - 70 800 800 350 350 1.1 5.5 75 808 816 400 410 1.4 - 80 mV kHz V % % VIN Rising Edge - 3.8 - - 430 4.3 - V mV VFB = 1.0 V, No Switching, VIN = 13.2 V VFB = 1.0 V, COMP = 0 V, VIN = 13.2 V VFB = 1.0 V, No Switching, VIN = 13.2 V 1.0 - 0.1 - 4.0 - 10.0 - 1.0 mA mA mA Conditions VIN - GND VBST - GND Min 4.5 4.5 Typ Max 13.2 26.5 Unit V V
min/max values unless otherwise noted.)
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TYPICAL CHARACTERISTICS
5.0 4.5 INPUT CURRENT (mA) INPUT CURRENT (mA) 4.0 3.5 3.0 2.5 2.0 -60 -40 -20 VCC = 5 V VCC = 12 V 25 23 21 19 17 15 13 11 0 20 40 60 80 100 120 140 9 0 VCC = 5 V 10 20 30 40 50 60 70 VCC = 12 V
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 4. ICC vs. Temperature
SOFT-START SOURCING CURRENT (mA) 14 13 Vref, REFERENCE (mV) 12 11 10 9 8 808 806 804 802 800 798 796 794 0 10 20 30 40 50 60 TJ, JUNCTION TEMPERATURE (C) 70 792 0
Figure 5. Input Current Switching vs. Temperature
10
20
30
40
50
60
70
Figure 6. Soft-Start Sourcing Current vs. Temperature
375 365 DUTY CYCLE (%) 355 345 335 325 6.0 5.0 4.0 3.0 2.0 1.0 0
TJ, JUNCTION TEMPERATURE (C)
Figure 7. Reference Voltage (Vref) vs. Temperature
SCP THRESHOLD (mV)
VCC = 12 V
VCC = 5 V
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 8. SCP Threshold vs. Temperature
Figure 9. Minimum Active Duty Cycle vs. Temperature
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NCP3125
TYPICAL CHARACTERISTICS
76 75.5 DUTY CYCLE (%) VCC = 12 V 75 74.5 74 73.5 73 VCC = 5 V
0
10
20
30
40
50
60
70
TJ, JUNCTION TEMPERATURE (C)
Figure 10. Duty Cycle Maximum vs. Temperature
100 95 90 EFFICIENCY (%) 80 75 70 65 60 55 50 0 85
5.0 V Output
100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 1.8 V 1.2 V 1.1 V 1.0 V 2.5 V Output
1.8 V 3.3 V 2.5 V
1.5 V 1.2 V 1.1 V 1.0 V
1.5 V
0.5
1
1.5 2 2.5 LOAD CURRENT (A)
3
3.5
4
0
0.5
1
1.5 2 2.5 LOAD CURRENT (A)
3
3.5
4
Figure 11. Efficiency (VIN = 12 V) vs. Load Current
4.5 4 OUTPUT CURRENT (A) 3.5 3 2.5 2 1.5 1 0.5 0 25 35 45 55 65 75 85 5.0 V 1.8 V 4.5 1.2 V OUTPUT CURRENT (A) 3.3 V 4 3.5 3 2.5 2 1.5 1 0.5 0 25
Figure 12. Efficiency (VIN = 5 V) vs. Load Current
1.2 V
3.3 V
1.8 V
35
45
55
65
75
85
TA, AMBIENT TEMPERATURE
TA, AMBIENT TEMPERATURE
Figure 13. Derating Curve 5 V/6 V Input
Figure 14. Derating Curve 12 V Input
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NCP3125
General
COMP Disable 2N7002E Gate Signal Enable
The NCP3125 is a PWM synchronous buck regulator intended to supply up to a 4 A load for DC-DC conversion from 5 V and 12 V buses. The NCP3125 is a regulator that has integrated high-side and low-side NMOSFETs switches. The output voltage of the converter can be precisely regulated down to 800 mV 1.0% when the VFB pin is tied to VOUT. The switching frequency is internally set to 350 kHz. A high gain operational transconductance amplifier (OTA) is used for voltage mode control of the power stage.
Duty Ratio and Maximum Pulse Width Limits
COMP Disable Base Signal Enable
In steady state DC operation, the duty ratio will stabilize at an operating point defined by the ratio of the input to the output voltage. The device can achieve a 75% duty ratio. The NCP3125 has a preset off-time of approximately 150 ns, which ensures that the bootstrap supply is charged every switching cycle. The preset off time does not interfere with the conversion of 12 V to 0.8 V. The input voltage range for both VIN and BST is 4.5 V to 13.2 V with respect to GND and VSW. Although BST is rated at 13.2 V with respect to VSW, it can also tolerate 26.5 V with respect to GND.
External Enable/Disable Input Voltage Range (VIN and BST)
MMBT3904
Figure 15. Recommended Disable Circuits Power Sequencing
Once the input voltage has exceeded the boost and UVLO threshold at 3 V and VIN threshold at 4 V, the COMP pin starts to rise. The VSW node is tri-stated until the COMP voltage exceeds 0.9 V. Once the 0.9 V threshold is exceeded, the part starts to switch and the part is considered enabled. When the COMP pin voltage is pulled below the 400 mV threshold, it disables the PWM logic, the top MOSFET is driven off, and the bottom MOSFET is driven on. In the disabled mode, the OTA output source current is reduced to 10 mA. When disabling the NCP3125 using the COMP / Disable pin, an open collector or open drain drive should be used as shown in Figure 15:
Power sequencing can be achieved with NCP3125 using two general purpose bipolar junction transistors or MOSFETs. An example of the power sequencing circuit using the external components is shown in Figure 16.
VSW NCP3125 FB1 COMP 1.0V VIN VSW NCP3125 FB1 COMP 3.3 V
Figure 16. Power Sequencing Input Voltage Shutdown Behavior
Input voltage shutdown occurs when the IC stops switching because the input supply reaches UVLO threshold. Undervoltage Lockout (UVLO) is provided to ensure that unexpected behavior does not occur when VCC is too low to support the internal rails and power the converter. The UVLO is set to permit operation when converting from an input voltage of 5 V. If the UVLO is tripped, switching stops, the internal SS is discharged, and all MOSFET gates are driven low. The VSW node enters a high impedance state and the output capacitors discharge through the load with no ringing on the output voltage.
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NCP3125
Overcurrent Threshold Setting
0.9 V COMP
BG
TG
NCP3125 overcurrent threshold can be set from 50 mV to 550 mV, by adding a resistor (RSET) between ISET and GND. During a short period of time following VIN rising over UVLO threshold, an internal 10 mA current (IOCSET) is sourced from the ISET pin, creating a voltage drop across RSET. The voltage drop is compared against a stepped internal voltage ramp. Once the internal stepped voltage reaches the RSET voltage, the value is stored internally until power is cycled. The overall time length for the OC setting procedure is approximately 9 ms. Connecting an RSET resistor between ISET and GND, the programmed threshold will be:
I OCth + I OCSET * R SET R DS(on) 4.2 A + 10 mA * 21 kW 50 mW
(eq. 1)
Figure 17. Enable/Disable Driver State Diagram External Soft-Start
The NCP3125 features an external soft-start function, which reduces inrush current and overshoot of the output voltage. Soft-start is achieved by using the internal current source of 10.5 mA (typ), which charges the external integrator capacitor of the OTA. Figure 18 is a typical soft-start sequence. The sequence begins once VIN and VBST surpass their UVLO thresholds and OCP programming is complete. The current sourced out of the COMP pin continually increases the voltage until regulation is reached. Once the voltage reaches 400 mV logic is enabled. When the voltage exceeds 900 mV, switching begins. Current is sourced out of the COMP pin, placing the regulator into open loop operation until 800 mV is sensed at the FB pin. Once 800 mV is sensed at the FB pin, open loop operation ends and closed loop operation begins. In closed loop operation, the OTA is capable of sourcing and sinking 120 mA.
4.2 V VCC 0.9 V COMP VFB BG TG BG Comparator DAC Voltage BG Comparator Output 500 mV 50 mV 3.85 V
IOCSET = Sourced current IOCth = Current trip threshold RDS(on) = On resistance of the low side MOSFET RSET = Current set resistor The RSET values range from 5 kW to 55 kW. If RSET is not connected, the device switches the OCP threshold to a fixed 375 mV value. An internal safety clamp on ISET is triggered as soon as ISET voltage reaches 700 mV, enabling the 375 mV fixed threshold and ending the OCP setting period. The current trip threshold tolerance is 25 mV. The accuracy is best at the highest set point (550 mV). The accuracy will decrease as the set point decreases. MOSFET tolerances with temperature and input voltage will vary the over current set threshold operating point. A graph of the typical current limit set thresholds at 4.5 V and 12 V is shown in Figure .
7 6.5 OUTPUT CURRENT (A) 6 5.5 5 4.5 4 3.5 3 2.5 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 RSET (kW) 5V 12 V
Vout UVLO POR Current Soft-Start Normal Operation Delay Trip Set COMP Delay UVLO
Figure 19. RSET Value for Output Current
Figure 18. Soft-Start Sequence
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Current Limit Protection
BG Drive
Low Side MOSFET Current
PHASE
0V VOCTH
APPLICATION SECTION
Design Procedure
When starting the design of a buck regulator, it is important to collect as much information as possible about the behavior of the input and output before starting the design. ON Semiconductor has a Microsoft Excel(R) based design tool available online under the design tools section of the NCP3125 product page. The tool allows you to capture your design point and optimize the performance of your regulator based on your design criteria.
Table 4. DESIGN PARAMETERS
Design Parameter Input voltage Output voltage Input ripple voltage Output ripple voltage Output current rating Operating frequency (VIN) (VOUT) (VINRIPPLE) (VOUTRIPPLE) (IOUT) (FSW) Example Value 10.8 V to 13.2 V 3.3 V 300 mV 60 mV 4A 350 kHz
VOUT, VIN, the Low Side Switch Voltage Drop VLSD, and the High Side Switch Voltage Drop VHSD.
F SW + 1 T D+ D+ T ON T and (1 * D) + OFF T T
(eq. 2) (eq. 3)
V OUT ) V LSD V 3.3 V [ D + OUT 27.5% + V IN * V HSD ) V LSD V IN 12 V
(eq. 4)
D FSW T TOFF TON VHSD VIN VLSD VOUT
Inductor Selection
The buck converter produces input voltage VIN pulses that are LC filtered to produce a lower DC output voltage VOUT. The output voltage can be changed by modifying the on time relative to the switching period T or switching frequency. The ratio of high side switch on time to the switching period is called duty ratio D. Duty ratio can also be calculated using
When selecting an inductor, the designer can employ a rule of thumb for the design where the percentage of ripple current in the inductor should be between 10% and 40%. When using ceramic output capacitors, the ripple current can be greater because the ESR of the output capacitor is smaller, thus a user might select a higher ripple current. However,
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+
- VOCTH
In case of a short circuit or overload, the low-side (LS) FET will conduct large currents. The regulator will latch off, protecting the load and MOSFETs from excessive heat and damage. Low-side RDS(on) sense is implemented at the end of each LS-FET turn-on duration to sense the current. While the low side MOSFET is on, the VSW voltage is compared to the user set internally generated OCP trip voltage. If the VSW voltage is lower than OCP trip voltage, an overcurrent condition occurs and a counter counts consecutive current trips. If the counter reaches 7, the PWM logic and both HS-FET and LS-FET are turned off. The regulator has to go through a Power On Reset (POR) cycle to reset the OCP fault as shown in Figure 20.
Current BG Flow
Figure 20. Current Limit Trip
= Duty cycle = Switching frequency = Switching period = High side switch off time = High side switch on time = High side switch voltage drop = Input voltage = Low side switch voltage drop = Output voltage
NCP3125
when using electrolytic capacitors, a lower ripple current will result in lower output ripple due to the higher ESR of electrolytic capacitors. The ratio of ripple current to maximum output current is given in Equation 5.
ra + DI Iout
(eq. 5)
I PK + I OUT @ 1 )
ra 30% 4.6 A + 4 A @ 1 ) 2 2
(eq. 8)
DI = Ripple current IOUT = Output current ra = Ripple current ratio Using the ripple current rule of thumb, the user can establish acceptable values of inductance for a design using Equation 6.
L OUT + V OUT @ (1 * D) I OUT @ ra @ F SW
3.3 V 5.7 mH + @ (1 * 27.5%) 4 A @ 30% @ 350 kHz
(eq. 6)
D FSW IOUT LOUT ra
18 16 INDUCTANCE (mH) 14 12 10 8 6 4
= Duty ratio = Switching frequency = Output current = Output inductance = Ripple current ratio
IOUT = Output current IPK = Inductor peak current ra = Ripple current ratio A standard inductor should be found so the inductor will be rounded to 5.6 mH. The inductor should also support an RMS current of 4.01 A and a peak current of 4.6 A. The final selection of an output inductor has both mechanical and electrical considerations. From a mechanical perspective, smaller inductor values generally correspond to smaller physical size. Since the inductor is often one of the largest components in the regulation system, a minimum inductor value is particularly important in space constrained applications. From an electrical perspective, the maximum current slew rate through the output inductor for a buck regulator is given by Equation 9.
SlewRate LOUT + V IN * V OUT L OUT 1.53 A 12 V * 3.3 V + ms 5.6 mH
(eq. 9)
VIN = 12 V
Selected VIN = 4.2 V VIN = 8 V
2 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 CURRENT RIPPLE RATIO (%)
LOUT = Output inductance VIN = Input voltage VOUT = Maximum output voltage Equation 9 implies that larger inductor values limit the regulator's ability to slew current through the output inductor in response to output load transients. Consequently, output capacitors must supply the load current until the inductor current reaches the output load current level. Reduced inductance to increase slew rates results in larger values of output capacitance to maintain tight output voltage regulation. In contrast, smaller values of inductance increase the regulator's maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current. The peak-to-peak ripple current for NCP3125 is given by the following equation:
Ipp + V OUT (1 * D) L OUT @ F SW 1.2 A + 3.3 V (1 * 27.5%) 5.6 mH @ 350 kHz
(eq. 10)
Figure 21. Inductance vs. Current Ripple Ratio
When selecting an inductor, the designer must not exceed the current rating of the part. To keep within the bounds of the part's maximum rating, a calculation of the RMS and peak inductor current is required.
I RMS + I OUT @ 1 ) ra 12 1) 30% 2 12
2
(eq. 7)
4.01 A + 4 A *
IOUT IRMS ra
= Output current = Inductor RMS current = Ripple current ratio
D = Duty ratio FSW = Switching frequency Ipp = Peak-to-peak current of the inductor LOUT = Output inductance VOUT = Output voltage From Equation 10 it is clear that the ripple current increases as LOUT decreases, emphasizing the trade-off between dynamic response and ripple current. The power dissipation of an inductor falls into two categories: copper and core losses. The copper losses can be further categorized into DC losses and AC losses. A good first order approximation of the inductor losses can be made using the DC resistance as shown below:
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LP _DC + I RMS 2 @ DCR 281 mW + 4.01 2 @ 17.5 mW
(eq. 11)
IRMS = Inductor RMS current DCR = Inductor DC resistance LPCU_DC = Inductor DC power dissipation The core losses and AC copper losses will depend on the geometry of the selected core, core material, and wire used. Most vendors will provide the appropriate information to make accurate calculations of the power dissipation at which point the total inductor losses can be captured by the equation below:
LP tot + LP CU_DC ) LP CU_AC ) LP Core 303 mW + 281 mW ) 1 mW ) 21 mW
(eq. 12)
The ESL of capacitors depends on the technology chosen, but tends to range from 1 nH to 20 nH, where ceramic capacitors have the lowest inductance and electrolytic capacitors have the highest. The calculated contributing voltage ripple from ESL is shown for the switch on and switch off below:
V ESLON + ESL * Ipp * F SW D
(eq. 15)
15.27 mV + V ESLOFF +
10 nH * 1.2 A * 350 kHz 27.5%
LPCU_DC LPCU_AC LPCore
= Inductor DC power dissipation = Inductor AC power dissipation = Inductor core power dissipation
(1 * D ) 10 nH * 1.2 A * 350 kHz 5.79 mV + 1 * 27.5%
ESL * Ipp * F SW
(eq. 16)
Output Capacitor Selection
The important factors to consider when selecting an output capacitor are DC voltage rating, ripple current rating, output ripple voltage requirements, and transient response requirements. The output capacitor must be rated to handle the ripple current at full load with proper derating. The RMS ratings given in datasheets are generally for lower switching frequency than used in switch mode power supplies, but a multiplier is usually given for higher frequency operation. The RMS current for the output capacitor can be calculated below:
Co RMS + I OUT @ ra 12 0.346 A + 4 A 30% 12
(eq. 13)
D = Duty ratio ESL = Capacitor inductance FSW = Switching frequency Ipp = Peak-to-peak current The output capacitor is a basic component for the fast response of the power supply. For the first few microseconds of a load transient, the output capacitor supplies current to the load. Once the regulator recognizes a load transient, it adjusts the duty ratio, but the current slope is limited by the inductor value. During a load step transient, the output voltage initially drops due to the current variation inside the capacitor and the ESR (neglecting the effect of the ESL).
DV OUT*ESR + I TRAN Co ESR 115 mV + 2.3
(eq. 17)
50 mW
CoRMS = Output capacitor RMS current IOUT = Output current ra = Ripple current ratio The maximum allowable output voltage ripple is a combination of the ripple current selected, the output capacitance selected, the Equivalent Series Inductance (ESL), and Equivalent Series Resistance (ESR). The main component of the ripple voltage is usually due to the ESR of the output capacitor and the capacitance selected, which can be calculated as shown in Equation 14:
V ESR_C + I OUT * ra * Co ESR ) 1 8 * F SW * C OUT 1 8 * 350 kHz * 470 mF
= Output capacitor Equivalent Series Resistance ITRAN = Output transient current DVOUT_ESR = Voltage deviation of VOUT due to the effects of ESR A minimum capacitor value is required to sustain the current during the load transient without discharging it. The voltage drop due to output capacitor discharge is given by the following equation:
DV OUT*DIS + I TRAN 2
2
CoESR
L OUT V IN * V OUT
2
D MAX C OUT 2.3 A 2 75%
(eq. 18)
(eq. 14)
4.9 mV +
5.6 mH
470 mF
12 V * 3.3 V
60.91 mV + 4 * 30% * 50 mW )
CoESR COUT FSW IOUT ra
= Output capacitor ESR = Output capacitance = Switching frequency = Output current = Ripple current ratio
COUT = Output capacitance DMAX = Maximum duty ratio ITRAN = Output transient current LOUT = Output inductor value VIN = Input voltage VOUT = Output voltage DVOUT_DIS = Voltage deviation of VOUT due to the effects of capacitor discharge
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In a typical converter design, the ESR of the output capacitor bank dominates the transient response. Please note that DVOUT-DIS and DVOUT-ESR are out of phase with each other, and the larger of these two voltages will determine the maximum deviation of the output voltage (neglecting the effect of the ESL).
Input Capacitor Selection
Starting with the high-side MOSFET, the power dissipation can be approximated from:
P D_HS + P COND ) P SW_TOT
(eq. 21)
The input capacitor has to sustain the ripple current produced during the on time of the upper MOSFET, so it must have a low ESR to minimize the losses. The RMS value of the input ripple current is:
Iin RMS + I OUT D (1 * D)
(eq. 19)
PCOND = Conduction power losses PSW_TOT = Total switching losses PD_HS = Power losses in the high side MOSFET The first term in Equation 21 is the conduction loss of the high-side MOSFET while it is on.
P COND + I RMS_HS
2
@ R DS(on)_HS
(eq. 22)
1.79 A + 4 A * 27.5 * (1 * 27.5)
D = Duty ratio IINRMS = Input capacitance RMS current IOUT = Load current The equation reaches its maximum value with D = 0.5. Loss in the input capacitors can be calculated with the following equation:
P CIN + CIN ESR * IiN RMS
2
IRMS_HS = RMS current in the high-side MOSFET RDS(on)_HS = On resistance of the high-side MOSFET Pcond = Conduction power losses Using the ra term from Equation 5, IRMS becomes:
I RMS_HS + I OUT @ D@ 1) ra 2 12
(eq. 23)
2
(eq. 20)
32 mW + 10 mW * 1.79 A
CINESR
= Input capacitance Equivalent Series Resistance IINRMS = Input capacitance RMS current PCIN = Power loss in the input capacitor Due to large di/dt through the input capacitors, electrolytic or ceramics should be used. If a tantalum must be used, it must be surge protected, otherwise, capacitor failure could occur. MOSFET power dissipation, package size, and the thermal environment drive power supply design. Once the dissipation is known, the thermal impedance can be calculated to prevent the specified maximum junction temperatures from being exceeded at the highest ambient temperature. Power dissipation has two primary contributors: conduction losses and switching losses. The high-side MOSFET will display both switching and conduction losses. The switching losses of the low side MOSFET will not be calculated as it switches into nearly zero voltage and the losses are insignificant. However, the body diode in the low-side MOSFET will suffer diode losses during the non-overlap time of the gate drivers.
IRMS_HS = High side MOSFET RMS current IOUT = Output current D = Duty ratio ra = Ripple current ratio The second term from Equation 21 is the total switching loss and can be approximated from the following equations.
P SW_TOT + P SW ) P DS ) P RR
(eq. 24)
Power MOSFET Dissipation
PDS = High side MOSFET drain source losses PRR = High side MOSFET reverse recovery losses PSW = High side MOSFET switching losses PSW_TOT = High side MOSFET total switching losses The first term for total switching losses from Equation 24 are the losses associated with turning the high-side MOSFET on and off and the corresponding overlap in drain voltage and current.
P SW + P TON ) P TOFF + 1 @ I OUT @ V IN @ F SW @ t RISE ) t FALL 2
(eq. 25)
FSW IOUT tFALL tRISE VIN PSW PTON PTOFF
= Switching frequency = Load current = MOSFET fall time = MOSFET rise time = Input voltage = High side MOSFET switching losses = Turn on power losses = Turn off power losses
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NCP3125
When calculating the rise time and fall time of the high side MOSFET it is important to know the charge characteristic shown in Figure 22. FSW = Switching frequency PRR = High side MOSFET reverse recovery losses QRR = Reverse recovery charge VIN = Input voltage The low-side MOSFET turns on into small negative voltages so switching losses are negligible. The low-side MOSFET's power dissipation only consists of conduction loss due to RDS(on) and body diode loss during the non-overlap periods.
P D_LS + P COND ) P BODY
(eq. 30)
Vth
PBODY = Low side MOSFET body diode losses PCOND = Low side MOSFET conduction losses PD_LS = Low side MOSFET losses Conduction loss in the low-side MOSFET is described as follows:
Figure 22. MOSFET Switching Characteristics Q GD I G1 Q GD V BST * V TH R HSPU ) R G P COND + I RMS_LS
2
@ R DS(on)_LS
(eq. 31)
t RISE +
+
(eq. 26)
IRMS_LS RDS(on)_LS PCOND
= RMS current in the low side = Low-side MOSFET on resistance = High side MOSFET conduction losses
2 (1 * D) @ 1 ) ra 12
IG1 QGD RHSPU RG tRISE VBST VTH
t FALL + I G2
= Output current from the high-side gate drive = MOSFET gate to drain gate charge = Drive pull up resistance = MOSFET gate resistance = MOSFET rise time = Boost voltage = MOSFET gate threshold voltage
Q GD + Q GD V BST * V TH R HSPD ) R G
(eq. 27)
I RMS_LS + I OUT @
(eq. 32)
D = Duty ratio IOUT = Load current IRMS_LS = RMS current in the low side ra = Ripple current ratio The body diode losses can be approximated as:
P BODY + V FD @ I OUT @ F SW @ NOL LH ) NOL HL (eq. 33)
IG2 = Output current from the low-side gate drive QGD = MOSFET gate to drain gate charge RG = MOSFET gate resistance RHSPD = Drive pull down resistance tFALL = MOSFET fall time VBST = Boost voltage VTH = MOSFET gate threshold voltage Next, the MOSFET output capacitance losses are caused by both the high-side and low-side MOSFETs, but are dissipated only in the high-side MOSFET.
2 P DS + 1 @ C OSS @ V IN @ F SW 2
FSW IOUT NOLHL NOLLH PBODY VFD
= Switching frequency = Load current = Dead time between the high-side MOSFET turning off and the low-side MOSFET turning on, typically 50 ns = Dead time between the low-side MOSFET turning off and the high-side MOSFET turning on, typically 50 ns = Low-side MOSFET body diode losses = Body diode forward voltage drop
Control Dissipation
(eq. 28)
The control portion of the IC power dissipation is determined by the formula below:
P C + I CC V IN
(eq. 34)
COSS = MOSFET output capacitance at 0V FSW = Switching frequency PDS = MOSFET drain to source charge losses VIN = Input voltage Finally, the loss due to the reverse recovery time of the body diode in the low-side MOSFET is shown as follows:
P RR + Q RR @ V IN @ F SW
(eq. 29)
ICC = Control circuitry current draw PC = Control power dissipation VIN = Input voltage Once the IC power dissipations are determined, the designer can calculate the required thermal impedance to maintain a specified junction temperature at the worst case
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NCP3125
ambient temperature. The formula for calculating the junction temperature with the package in free air is:
T J + T A ) P D @ R qJA
(eq. 35)
PD RqJA
= Power dissipation of the IC = Thermal resistance junction to ambient of the regulator package TA = Ambient temperature TJ = Junction temperature As with any power design, proper laboratory testing should be performed to ensure the design will dissipate the required power under worst case operating conditions. Variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading, and component variations (i.e., worst case MOSFET RDS(on)).
FSW = Switching frequency FESR = Output capacitor ESR zero frequency If the criteria is not met, the compensation network may not provide stability and the output power stage must be modified. Figure 23 shows a pseudo Type III transconductance error amplifier.
ZIN
CF IEA R1 RF
ZFB CC CP Gm R2
Compensation Network
To create a stable power supply, the compensation network around the transconductance amplifier must be used in conjunction with the PWM generator and the power stage. Since the power stage design criteria is set by the application, the compensation network must correct the over all system response to ensure stability. The output inductor and capacitor of the power stage form a double pole at the frequency as shown in Equation 36:
F LC + 1 2p L OUT 2p C OUT 1 5.6 mH 470 mF
(eq. 36)
RC VREF
Figure 23. Pseudo Type III Transconductance Error Amplifier
3.102 kHz +
COUT FLC
= Output capacitor = Double pole inductor and capacitor frequency LOUT = Output inductor value The ESR of the output capacitor creates a "zero" at the frequency as shown in Equation 37:
F ESR + 6.772 kHz + 2p 2p 1 CO ESR 1 0.050 mW 470 mF C OUT
(eq. 37)
COESR = Output capacitor ESR COUT = Output capacitor FLC = Output capacitor ESR frequency The two equations above define the bode plot that the power stage has created or open loop response of the system. The next step is to close the loop by considering the feedback values. The closed loop crossover frequency should be greater than the FLC and less than 1/5 of the switching frequency, which would place the maximum crossover frequency at 70 kHz. Further, the calculated FESR frequency should meet the following:
F ESR t F SW 5
(eq. 38)
The compensation network consists of the internal OTA and the impedance networks ZIN (R1, R2, RF, and CF) and external ZFB (RC, CC, and CP). The compensation network has to provide a closed loop transfer function with the highest 0 dB crossing frequency to have fast response and the highest gain in DC conditions to minimize the load regulation issues. A stable control loop has a gain crossing with -20 dB/decade slope and a phase margin greater than 45. Include worst-case component variations when determining phase margin. To start the design, a resistor value should be chosen for R2 from which all other components can be chosen. A good starting value is 10 kW. The NCP3125 allows the output of the DC-DC regulator to be adjusted down to 0.8 V via an external resistor divider network. The regulator will maintain 0.8 V at the feedback pin. Thus, if a resistor divider circuit was placed across the feedback pin to VOUT, the regulator will regulate the output voltage proportional to the resistor divider network in order to maintain 0.8 V at the FB pin.
VOUT R1 FB R2
Figure 24. Feedback Resistor Divider
The relationship between the resistor divider network above and the output voltage is shown in Equation 39:
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NCP3125
R2 + R1 @ V REF V OUT * V REF
(eq. 39)
R1 = Top resistor divider R2 = Bottom resistor divider VOUT = Output voltage VREF = Regulator reference voltage The most frequently used output voltages and their associated standard R1 and R2 values are listed in Table 5.
Table 5. OUTPUT VOLTAGE SETTINGS
VO (V) 0.8 1.2 1.5 1.8 2.5 3.3 5.0 R1 (kW) 1.0 4.99 10 12.7 21.5 31.6 52.3 R2 (kW) Open 10 11.5 10.2 10 10 10
The compensation components for the Pseudo Type III Transconductance Error Amplifier can be calculated using the method described below. The method serves to provide a good starting place for compensation of a power supply. The values can be adjusted in real time using the compensation tool comp calc, available for download at ON Semiconductor's website. The value of the feed through resistor should always be at least 2X the value of R2 to minimize error from feed through noise. Using the 2X assumption, RF will be set to 20 kW and the feed through capacitor can be calculated as shown below:
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NCP3125
CF + R1 ) R2 2p R1 ) RF ) R2 RF ) R2 R1 f cross
(eq. 40)
0.96 nF +
31.6 kW ) 10 kW 2p 31.6 kW 20 kW ) 10 kW 20 kW ) 10 kW 31.6 kW 30 kHz
CF fcross R1 R2 RF
= Feed through capacitor = Crossover frequency = Top resistor divider = Bottom resistor divider = Feed through resistor
The cross over of the overall feedback occurs at FPO:
F PO + R1 ) RF (2p)
2
V ramp RF RF ) R1 FLC V IN
CF
2
R1 ) RF
R2 ) R1
(eq. 41)
1.152 kHz +
31.6 kW ) 20 kW (2p)
2
1.1 V 20 kW 20 kW ) 31.6 kW 3.102 kHz 12 V
(0.96)
2
31.6 kW ) 20 kW
10 kW ) 31.6 kW
CF FLC FPO R1 R2 RF VIN Vramp
= Feed through capacitor = Frequency of the output inductor and capacitor = Pole frequency = Top of resistor divider = Bottom of resistor divider = Feed through resistor = Input voltage = Peak-to-peak voltage of the ramp
The cross over combined compensation network can be used to calculate the transconductance output compensation network as follows:
CC + 84 nF + 1 F PO 1 1.152 kHz R2 R2 R1 gm
(eq. 42)
10 kW 10 kW ) 31.6 kW
4 ms
CC FPO gm R1 R2
= Compensation capacitor = Pole frequency = Transconductance of amplifier = Top of resistor divider = Bottom of resistor divider
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NCP3125
RC + 1 2 F LC CC 2 2 ) f cross CO ESR 1 2 3.102 kHz 84 nF 2 2 ) 30 kHz 0.05 mW 470 mF C OUT
(eq. 43)
1.355 kW +
CC COESR COUT fcross FLC RC
= Compensation capacitance = Output capacitor ESR = Output capacitance = Crossover frequency = Output inductor and capacitor frequency = Compensation resistor
C P + C OUT
CO ESR RC 2 p
(eq. 44)
2.76 nF + 470 mF
0.05 mW 1.355 kW 2*p
COESR COUT CP RC
= Output capacitor ESR = Output capacitor = Compensation pole capacitor = Compensation resistor
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NCP3125
Assuming an output capacitance of 470 mF in parallel with 22 mF with a crossover frequency of 35 kHz, the compensation values for common output voltages can be calculated as shown in Table 6:
Table 6. COMPENSATION VALUES
Vin (V) 12 12 12 12 12 12 12 5 5 5 5 5 Vout (V) 0.8 1.2 1.5 1.8 2.5 3.3 5.0 0.8 1.2 1.5 1.8 2.5 Lout (mF) 2.2 2.7 2.7 3.9 4.7 5.6 6.8 1.8 2.7 2.7 3.3 3.3 RF (kW) X 20 20 20 20 20 20 20 20 20 20 20 Cf (nF) X 1 1 1 1 1 1 1 1 1 1 1 Cc (nF) 150 100 100 120 82 68 47 68 56 39 33 27 Rc (kW) 0.243 0.412 0.487 0.806 1.07 1.4 1.96 0.453 0.953 1.15 1.5 1.82 Cp (nF) 5.6 2.7 2.7 1.8 1.5 1.2 0.82 1 1 0.82 0.68 0.56
Vout Vcomp V
900 mV
Figure 25. Soft-Start Ramp
The delay from the charging of the compensation network to the bottom of the ramp is considered tssdelay. The total delay time is the addition of the current set delay and tssdelay, which in this case is 9 ms and 7.45 ms respectively, for a total of 16.45 ms.
Calculating Input Inrush Current
Calculating Soft-Start Time
To calculate the soft-start delay and soft-start time, the following equations can be used.
t SSdelay + CP ) CC I SS 2.83 nF ) 80 nF 10 mA 0.9 V
(eq. 45)
The input inrush current has two distinct stages: input charging and output charging. The input charging of a buck stage is usually not controlled, and is limited only by the input RC network, and the output impedance of the upstream power stage. If the upstream power stage is a perfect voltage source, then the input charge inrush current can be depicted as shown in Figure 26 and calculated as:
IPK
7.45 ms +
0.9 V
CP = Compensation pole capacitor CC = Compensation capacitor ISS = Soft-start current The time the output voltage takes to increase from 0 V to a regulated output voltage is tss as shown in Equation 46:
t SS + CP ) CC I SS 2.83 nF ) 80 nF 10 mA 27.5% D V ramp
(eq. 46)
Figure 26. Input Charge Inrush Current V IN CIN ESR
(eq. 47)
I ICinrush_PK1 + 12 0.1
120 A + 1.1 V
2.51 ms +
CP CC D ISS tSS Vramp
= Compensation pole capacitor = Compensation capacitor = Duty ratio = Soft-start current = Soft-start interval = Peak-to-peak voltage of the ramp
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NCP3125
Inrush Current Load NCP3125 OR
I ICinrush_RMS1 +
V IN CIN ESR
1*
1
t DELAY_TOTAL CINESR CIN
e
0.316 5
CIN ESR
C IN
(eq. 48)
t DELAY_TOTAL 1
380 mA +
12 V 0.1 W 5
Figure 27. Load Connected to the Output Stage
1*
e
0.316
16.45 ms 0.1W 330 mF
0.1 W
330 mF
If the load is resistive in nature, the output current will increase with soft-start linearly which can be quantified in Equation 50.
I CLR_RMS + 1 3 V OUT R OUT 3.3 V 10 W I CR_PK + V OUT R OUT
(eq. 50)
16.45 ms
CIN = Output capacitor CINESR = Output capacitor ESR tDELAY_TOTAL = Total delay interval = Input voltage VIN Once the tDELAY_TOTAL has expired, the buck converter starts to switch and a second inrush current can be calculated:
I OCinrush_RMS + C OUT ) C LOAD t SS V OUT D 3 ) I CL D
191 mA +
1 3
330 mA +
3.3 V 10 W
ROUT VOUT ICLR_RMS ICR_PK
= Output resistance = Output voltage = RMS resistor current = Peak resistor current
(eq. 49)
COUT = Total converter output capacitance CLOAD = Total load capacitance D = Duty ratio of the load = Applied load at the output ICL IOCinrush_RMS = RMS inrush current during start-up tSS = Soft-start interval VOUT = Output voltage From the above equation, it is clear that the inrush current is dependant on the type of load that is connected to the output. Two types of load are considered in Figure 27: a resistive load and a stepped current load.
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NCP3125
3.3 V
Layout Considerations
Output Voltage
Output Current tss
Figure 28. Resistive Load Current
As in any high frequency switching regulator, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. The interconnecting impedances should be minimized by using wide short printed circuit traces. The critical components should be located as close together as possible using ground plane construction or single point grounding. For optimal performance, the NCP3125 should have a layout similar to the one shown in Figure 30. An important note is that the input voltage to the NCP3125 should have local decoupling to PGND. The recommended decoupling for input voltage is a 1 mF general purpose ceramic capacitor and a 0.01 mF COG ceramic capacitor placed in parallel.
Top
Alternatively, if the output has an under voltage lockout, turns on at a defined voltage level, and draws a consistent current, then the RMS connected load current is:
I CLI+ V OUT * V OUT_TO V OUT I OUT
(eq. 51)
PGND
CC BST VIN AGND COMP RF FB PGND COG 0.01 uF
RISET
CP
RC
798 mA +
3.3 V * 1.2 V 3.3 V
1A
ISET VSW
R1 R2
CF
IOUT VOUT VOUT_TO
= Output current = Output voltage = Output voltage load turn on
1.0 V 3.3 V
1 .0 uF
AGND
PGND
CC RC
CF
R2 R1
PGND
Output Current
t
AGND
tss
Figure 29. Voltage Enable Load Current
Bottom Single Point Grounding Figure 30. Recommended Layout
If the inrush current is higher than the steady state input current during max load, then an input fuse should be rated accordingly using I2t methodology.
The typical applications are shown in Figures 31 and 32 for output electrolytic and ceramic bulk capacitors, respectively.
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IIIII IIIII IIIII IIII I IIIII II
COG 0.01 uF 1 .0 uF
RISET
II
CP RF
Output Voltage
AGND
BST VIN ISET VSW
COMP FB
II II
NCP3125
BST VSW
VIN C3 470uF 16V Vin C1 10uF 16V U1 NCP3125 4 3 2 1 AGND BST COMP VIN FB ISET PGND VSW 5 6 7 8 C11 0.01uF 16V R3 10R
D1 MMSD4148T1G CBST 10nF 25V C9 1nF 50V R9 100R
LOUT 3.9uH C7 470uF 6.3V
VOUT CHF 820pF 6.3V Vout
GND_IN CC 120n 10V
RC 806R CP COMP 1.8nF 50V
RSET 21k
C10 1uF 16V
CF 1nF 10V R1 12.7k
C4 22uF 6.3V
RF 20k FB
GND
GND
R2 10.2k
Figure 31. Standard Application 12 V to 1.8 V 4 A
BST
VSW
VIN U1 NCP3125 C1 10uF 16V C2 10uF 16V 4 5 AGND BST 3 6 COMP VIN 2 7 FB ISET 1 8 PGND VSW RSET 21k COMP CP 180pF 50V C11 0.01uF 16V R3 10R
D1 MMSD4148T1G CBST 10nF 25V C9 1nF 50V C10 1uF 16V R9 100R
Vin
LOUT 2.2uH C4 22uF 6.3V C5 47uF 6.3V GND GND VOUT RCR 100m CHF 820pF 6.3V
GND_IN
CC 390n 10V
RC 162R
CF 220pF 10V R1 12.7k
Vout
RF 6.8k FB
R2 10.2k
Figure 32. Ceramic Capacitor Application 12 V to 1.8 V 4 A
ORDERING INFORMATION
Device NCP3125ADR2G Package SOIC-8 (Pb-Free) Shipping 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NCP3125
PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AJ
-X- A
8 5
B
1
S
4
0.25 (0.010)
M
Y
M
-Y- G
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
C -Z- H D 0.25 (0.010)
M SEATING PLANE
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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NCP3125/D

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